DocumentCode :
1727815
Title :
World´s first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS
Author :
Naito, T. ; Ishida, T. ; Onoduka, T. ; Nishigoori, M. ; Nakayama, T. ; Ueno, Y. ; Ishimoto, Y. ; Suzuki, A. ; Chung, W. ; Madurawe, R. ; Wu, S. ; Ikeda, S. ; Oyamatsu, H.
Author_Institution :
Syst. LSI Div., Toshiba Corp., Oita, Japan
fYear :
2010
Firstpage :
219
Lastpage :
220
Abstract :
World´s first monolithically integrated Thin-Film-Transistor (TFT) SRAM configuration circuits over 90nm 9 layers of Cu interconnect CMOS is successfully fabricated at 300mm LSI mass production line for 3-dimensional Field Programmable Gate Arrays (3D-FPGA). This novel technology built over the 9th layer of Cu metal features aggressively scaled amorphous Si TFT having 180nm transistor gate length, 20nm gate oxide, fully silicided gate, S/D, all below 400C processing essential to not impact underlying Cu interconnects. Low temperature TFT devices show excellent NTFT/PTFT transistor Ion/Ioff ratios over 2000/100 respectively, operate at 3.3V, E-field scalable, and are stable for SRAM configuration circuits. We believe this 3D-TFT technology is a major breakthrough innovation to overcome the conventional CMOS device shrinking limitation.
Keywords :
CMOS integrated circuits; SRAM chips; copper; field programmable gate arrays; thin film transistors; Cu CMOS; LSI mass production line; NTFT-PTFT transistor; TFT SRAM; field programmable gate array; low temperature TFT device; monolithic 3D-FPGA; size 180 nm; size 300 mm; size 90 nm; thin-film-transistor; voltage 3.3 V; CMOS integrated circuits; CMOS technology; Copper; Logic gates; Random access memory; Thin film transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology (VLSIT), 2010 Symposium on
Conference_Location :
Honolulu
Print_ISBN :
978-1-4244-5451-8
Electronic_ISBN :
978-1-4244-5450-1
Type :
conf
DOI :
10.1109/VLSIT.2010.5556234
Filename :
5556234
Link To Document :
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