Title :
System in Package with Mounted Capacitor for Reduced Parasitic Inductance in Voltage Regulators
Author :
Hashimoto, T. ; Kawashima, T. ; Uno, T. ; Satou, Y. ; Matsuura, N.
Author_Institution :
Hitachi Res. Lab., Hitachi Ltd., Hitachi
Abstract :
A system in package (SiP) on which an input capacitor is mounted has been developed for voltage regulators. The SiP offers the world´s lowest power dissipation of 3.8 W at 1 MHz. Its parasitic inductance is 44% lower than SiPs with the input capacitor mounted on the PCB, due to a small loop from the input capacitor to the MOSFETs, which reduces power dissipation by 25% at the same peak voltage. The high-side MOSFET die is flipped so that the drain electrode faces up, facilitating the connection of the MOSFET to the input capacitor.
Keywords :
MOSFET; capacitors; electrodes; inductance; printed circuits; voltage regulators; PCB; drain electrode; high-side MOSFET die; mounted capacitor; parasitic inductance; peak voltage; power dissipation; system in package; voltage regulators; Capacitors; Circuits; Frequency; Inductance; MOSFETs; Packaging; Regulators; Switching loss; Virtual reality; Voltage;
Conference_Titel :
Power Semiconductor Devices and IC's, 2008. ISPSD '08. 20th International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
978-1-4244-1532-8
Electronic_ISBN :
978-1-4244-1533-5
DOI :
10.1109/ISPSD.2008.4538962
