DocumentCode
1727971
Title
Architectural optimizations for a floating point multiply-accumulate unit in a graphics pipeline
Author
Acken, Kevin P. ; Irwin, Mary Jane ; Owens, Robert M. ; Garga, Amulya K.
Author_Institution
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
fYear
1996
Firstpage
65
Lastpage
71
Abstract
Scientific visualization and virtual reality have pushed three-dimensional graphics engines to their limits for updating scenes in real-time. One bottleneck of graphic systems is the transformation of an object´s vertices into normalized space based on an evaluated transformation stack. This operation as often done in floating point, requiring a fast floating point multiply-accumulate unit. This paper presents architectural optimizations to a graphics pipeline floating point multiply-accumulate unit by using block floating point and parallelism to bypass or merge trivial operations in the matrix multiplications
Keywords
computer graphics; data visualisation; floating point arithmetic; matrix multiplication; virtual reality; architectural optimizations; floating point multiply-accumulate unit; graphics pipeline; matrix multiplications; normalized space; parallelism; scientific visualization; three-dimensional graphics engines; virtual reality; Computer graphics; Computer science; Engines; Hardware; Layout; Parallel processing; Pipeline processing; Virtual environment; Virtual reality; Visualization;
fLanguage
English
Publisher
ieee
Conference_Titel
Application Specific Systems, Architectures and Processors, 1996. ASAP 96. Proceedings of International Conference on
Conference_Location
Chicago, IL
ISSN
2160-0511
Print_ISBN
0-8186-7542-X
Type
conf
DOI
10.1109/ASAP.1996.542802
Filename
542802
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