Low-profile 3D silicon-on-silicon multi-chip assembly

The focus of this paper is multi-chip 3D silicon-on-silicon assembly using low-profile lead-free (Sn-Cu) solder interconnects. Thin 3D chips (~70 μm thick) containing tungsten TSVs and Cu wiring links were fabricated, diced and precision bonded to silicon substrates comprising ~20 μm tall lead-free solder “pancake” bumps on Ni UBMs. Modules with up to 24 thin 3D chips were fabricated and yield tested. The electrical effect of sequential joining was studied by adjusting the batch size of 3D chips joined in a single reflow. Four-point electrical measurements on single bump sites as well as chains having >;200 bumps/links show a clear shift in resistance as a function of the number of reflows, and this shift is correlated to the amount of Ni consumption at the solder/UBM interface. Yield chain data show a dramatic difference in the resistance shift depending on whether a chain is statistically “healthy” or “out of spec” after the chip is first joined. The results have significant implications for the cost-effective assembly of 3D silicon-on-silicon MCM and chip-to-wafer 3D chip-stacks.