• DocumentCode
    1728020
  • Title

    Reliability study of 3D-WLP through silicon via with innovative polymer filling integration

  • Author

    Bouchoucha, M. ; Chausse, P. ; Moreau, S. ; Chapelon, L.-L. ; Sillon, N. ; Thomas, O.

  • Author_Institution
    STMicroelectronics, Crolles, France
  • fYear
    2011
  • Firstpage
    567
  • Lastpage
    572
  • Abstract
    This paper deals with an innovative via-last TSV polymer filling process dedicated to straight (non-slopped), high aspect ratio (2:1 to 5:1) TSV, partially filled with copper. New polymers were investigated for this purpose. Firstly, the need for a polymer filling process is pointed out. Potential reliability issues added by this new process are developed through finite element modelling. Secondly, the filling process and the optimization phase in order to obtain a void free polymer inside the TSV are presented. A complete integration of polymer filling on electrical test vehicle is then performed. Finally, the impact of polymer filling on the TSV electrical performances is presented. Electrical tests are performed on chains of 10 and 100 TSV in order to check critical parameters such as electrical resistance. A reliability study of TSV polymer filling through JEDEC standard harsh temperature cycling is presented. First results of a comparison of the stack behaviour between a standard RDL polymer insulation and our innovative TSV polymer filling process is performed by means of morphological and electrical characterizations of the TSV before and after cycling.
  • Keywords
    filled polymers; finite element analysis; insulation; integrated circuit reliability; optimisation; three-dimensional integrated circuits; wafer level packaging; 3D-WLP through silicon via; JEDEC standard; RDL polymer insulation; TSV polymer filling; electrical resistance; electrical test vehicle; finite element modelling; harsh temperature cycling; innovative polymer filling integration; optimization; reliability; wafer level packaging; Copper; Filling; Insulation; Polymers; Resistance; Stress; Through-silicon vias;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st
  • Conference_Location
    Lake Buena Vista, FL
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-61284-497-8
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2011.5898568
  • Filename
    5898568