Title :
A fast and area efficient complimentary pass-transistor logic carry-skip adder
Author :
Strollo, Antonio G M ; Napoli, Ettore
Author_Institution :
Dept. of Electron., Univ. of Napoli, Italy
Abstract :
A two-level carry-skip adder using complementary pass-transistor logic is presented in this paper. The proposed adder is fast, area efficient and highly modular. It is compared with a two-level carry-skip adder using CMOS logic, and with a carry-lookahead adder automatically generated with the ALLIANCE CAD tools. SPICE simulations of the circuit extracted from the layout are used to evaluate the adder delay, while switch-level simulations are used to evaluate average power dissipation
Keywords :
CMOS logic circuits; SPICE; adders; carry logic; circuit analysis computing; delays; digital arithmetic; ALLIANCE AD tools; CPL logic; SPICE simulations; adder delay; area efficient design; average power dissipation; carry-skip adder; complimentary pass-transistor logic; switch-level simulations; Added delay; Adders; Automatic logic units; CMOS logic circuits; Circuit simulation; Frequency; Logic design; Multiplexing; SPICE; Switching circuits;
Conference_Titel :
Microelectronics, 1997. Proceedings., 1997 21st International Conference on
Conference_Location :
Nis
Print_ISBN :
0-7803-3664-X
DOI :
10.1109/ICMEL.1997.632941
