SIGGEN: A ΣΔ DAC autogeneration tool

This paper presents a tool dedicated to finding the optimum design solution for a ΣΔ DAC, based on a high level specification. The tool tackles the problem by first choosing the optimum ΣΔ modulator design by using a mixture of design equations and behavioral simulation. The analog part of the ΣΔ DAC is designed by choosing the optimum sizes of the devices and passive components from equation and simulation results. The tool enables a VHDL description of the interpolating stages and ΣΔ modulator to be generated. This facilitates automatic layout of the synthesized design. The layout of the analog part is manual but this is autoplaced and routed with the digital parts by commercial software. Simulation results and layout data for a ΣΔ DAC design are presented as well as measurements from a fifth order, 18-bit ΣΔ modulator. This design was fabricated on a 1.2u, double-metal double poly technology