A fast simulation framework for full-chip thermo-mechanical stress and reliability analysis of through-silicon-via based 3D ICs

In this work, we propose an efficient and accurate full-chip thermo-mechanical stress and reliability analysis framework. To the best of our knowledge this is the first such system which enables full-chip stress simulation as compared to existing commercial Finite Element Analysis (FEA) tools which can only simulate very small cross-sections at a time. Our approach is based on the linear superposition principle of stress tensors and the assumption that the stress field around a cylindrical TSV structure is symmetrically distributed. We compare the accuracy and run time of our simulation tool against the commercial FEA tool based on the number of TSVs under consideration. Our experimental results include stress maps produced by varying several parameters such as TSV liner material, size of the TSV landing pads and TSV dimensions. Finally, we also demonstrate our experimental results by simulating a full chip layout and varying the above parameters as well as by varying the chip operating temperature distribution.