DocumentCode
1728722
Title
A scalable chip set for MPEG2 real-time encoding
Author
Ngai, A. ; Sutton, J. ; Boice, C. ; Gebler, C.
Author_Institution
IBM Microelectron., Endicott, NY, USA
fYear
1996
Firstpage
193
Lastpage
198
Abstract
This is a description of an architecture for video compression based on the MPEG2 (MP@ML) standard. The chip set is comprised of 3 different devices. The architecture is scalable, and real-time MPEG2 systems could be built with one, two or all three chip solutions. The encoder includes an on-chip processor for programming options, and provides direct connections to external DRAM and SRAM.
Keywords
data compression; digital signal processing chips; real-time systems; telecommunication standards; video coding; MPEG2 real-time encoding; SRAM; architecture; direct connections; external DRAM; on-chip processor; programming options; scalable chip set; video compression; Computer aided instruction; Encoding; Entropy coding; Motion estimation; Performance evaluation; Random access memory; Silicon; Transform coding; Video coding; Video compression;
fLanguage
English
Publisher
ieee
Conference_Titel
Compcon '96. 'Technologies for the Information Superhighway' Digest of Papers
Conference_Location
Santa Clara, CA, USA
ISSN
1063-6390
Print_ISBN
0-8186-7414-8
Type
conf
DOI
10.1109/CMPCON.1996.501768
Filename
501768
Link To Document