Title :
Hybrid integration of silicon nanophotonics with 40nm-CMOS VLSI drivers and receivers
Author :
Thacker, Hiren D. ; Shubin, Ivan ; Luo, Ying ; Costa, Joannes ; Lexau, Jon ; Zheng, Xuezhe ; Li, Guoliang ; Yao, Jin ; Li, Jieda ; Patil, Dinesh ; Liu, Frankie ; Ho, Ron ; Feng, Dazeng ; Asghari, Mehdi ; Pinguet, Thierry ; Raj, Kannan ; Mitchell, James G.
Author_Institution :
Oracle Labs., San Diego, CA, USA
Abstract :
Oracle´s scalable hybrid integration technology platform enables continuing improvements in performance and energy efficiency of photonic bridge chips by leveraging advanced CMOS technologies with maximum flexibility, which is critical for developing ultralow power high-performance photonic interconnects for future computing systems. Herein, we report on our second generation of photonic bridge chips comprising electronic drivers and receivers built in 40 nm bulk CMOS technology attached to nanophotonic devices, fabricated using SOI-photonic and 130 nm SOI-CMOS photonic technologies. Hybrid integration by flip-chip bonding is enabled by microsolder bump interconnects scaled down from our previous generation effort and fabricated on singulated dies by a novel batch processing technique based on component embedding. Generation-on-generation, the hybrid integrated Tx and Rx bridge chips achieved 2.3× and 1.7× improvement in energy efficiency, respectively, while operating at 2× the datarate (10 Gbps).
Keywords :
CMOS integrated circuits; VLSI; driver circuits; elemental semiconductors; flip-chip devices; integrated circuit interconnections; integrated optoelectronics; low-power electronics; nanophotonics; optical interconnections; receivers; silicon; silicon-on-insulator; CMOS VLSI drivers; Oracle scalable hybrid integration technology platform; SOI-CMOS photonic technology; SOI-photonic; Si; batch processing technique; bit rate 10 Gbit/s; computing systems; electronic drivers; flip-chip bonding; microsolder bump interconnects; photonic bridge chips; receivers; silicon nanophotonic devices; size 130 nm; size 40 nm; ultralow power high-performance photonic interconnects; Arrays; Bridge circuits; CMOS integrated circuits; Integrated circuit interconnections; Photonics; Resists; Very large scale integration;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st
Conference_Location :
Lake Buena Vista, FL
Print_ISBN :
978-1-61284-497-8
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2011.5898607