Title :
A flexible motion estimation chip for variable size block matching
Author :
Berns, Jan Peter ; Noll, Tobias G.
Author_Institution :
Tech. Hochschule Aachen, Germany
Abstract :
A flexible block matching motion estimation architecture is described. The block size can be adaptively refined with blocks of 8×8, 16×16 and 32×32 pixels or can be set to one of these sizes without significant loss in efficiency in comparison with standard block matching. The chip performs block matching on a search area of ±15 vertically and horizontally for a block size of up to 32×32. For larger search areas devices can be cascaded. Full search can be processed as well as fast algorithms with an additional external RAM and a RISC processor. Sub-pel precision motion vectors can be derived using a smaller search area or cascading devices. The chip will have a computational power of more than 200 GOPS and a die size of 170 mm2 in a 0.5-μm CMOS technology
Keywords :
CMOS digital integrated circuits; digital signal processing chips; encoding; motion estimation; reduced instruction set computing; 0.5 micron; CMOS technology; RISC processor; block matching motion estimation architecture; external RAM; flexible motion estimation chip; variable size block matching; CMOS technology; Computer architecture; HDTV; Image coding; Image sequences; Motion detection; Motion estimation; Read-write memory; Reduced instruction set computing; Shape;
Conference_Titel :
Application Specific Systems, Architectures and Processors, 1996. ASAP 96. Proceedings of International Conference on
Conference_Location :
Chicago, IL
Print_ISBN :
0-8186-7542-X
DOI :
10.1109/ASAP.1996.542806
