DocumentCode :
1729045
Title :
Integration of fine-pitched Through-Silicon Vias and Integrated Passive Devices
Author :
Shariff, Dzafir ; Marimuthu, Pandi Chelvam ; Hsiao, Ken ; Asoy, Lily ; Yee, Chia Lai ; Oo, Aung Kyaw ; Buchanan, Keith ; Crook, Kath ; Wilby, Tony ; Burgess, Steve
Author_Institution :
STATS ChipPAC Ltd., Singapore, Singapore
fYear :
2011
Firstpage :
844
Lastpage :
848
Abstract :
This paper reports on a silicon interposer containing both Through-Silicon Vias [TSV] and Integrated Passive Devices [IPD]. The fine-pitched 30μm diameter × 100μm deep TSV connect the IPD on one side of the wafer with Re-Distribution Layer [RDL] metallization and solder bumps on the other. Such a platform provides great versatility for heterogeneous system integration and reduced form-factor packaging. Interposer manufacture is described and performance of integrated RF filters and resonators is assessed after reliability testing, including; high temperature stress, thermal cycling and accelerated stress test.
Keywords :
integrated circuit packaging; metallisation; passive networks; radiofrequency filters; radiofrequency integrated circuits; silicon; Si; accelerated stress test; fine pitched through silicon vias; heterogeneous system integration; high temperature stress; integrated RF filters; integrated passive devices; interposer manufacture; redistribution layer metallization; reduced form factor packaging; reliability testing; silicon interposer; solder bumps; thermal cycling; Band pass filters; Reliability; Resonator filters; Scattering parameters; Silicon; Testing; Through-silicon vias;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st
Conference_Location :
Lake Buena Vista, FL
ISSN :
0569-5503
Print_ISBN :
978-1-61284-497-8
Electronic_ISBN :
0569-5503
Type :
conf
DOI :
10.1109/ECTC.2011.5898609
Filename :
5898609
Link To Document :
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