Design, fabrication, and characterization of thermally isolating support membrane for low-noise SI JFET amplifier

The results of the development of a novel thermal isolation scheme for maintaining JFET amplifiers operating at 120 K in close proximity to "Spider Web" bolometer devices operating at 0.3 K is described. The thermal isolation was achieved by mounting the si-based JFETs on micro-machined silicon nitride membranes, optimized for this purpose. These membranes not only provide excellent thermal isolation, but are also mechanically robust and capable of withstanding stresses generated during thermal cycling, vibration and shock. The device configuration for the JFET readout stage consists of 24 dual Siliconix U401 JFETs mounted on the SiN thermal isolation membrane. The entire stage is mounted on a 4 K-cryostat for thermal dissipation purposes. Extensive testing showed that operation at temperatures around 120 K and at a frequency of 150 Hz, reduces the 1/f noise floor to approximately 10 n V/rtHz. An additional thermal dissipation constraint placed by the 4 K mounting state is that the total thermal dissipation from the JFET state be no more than 5.5 mW. We have successfully fabricated and delivered two JFET stages. Tests on the latest unit showed 23 functioning JFETs out of the 30 total, with a median noise level below 10 n V/rtHz for 5.5 mW thermal dissipation.