Title :
Reducing substrate noise coupling in a 3D-PICS Integrated Passive Device by localized P+ guard rings
Author :
Ben Salah, Miled ; Pasquet, Daniel ; Voiron, Frederic ; Descamps, Philippe ; Lefebvre, Joel ; Lesenechal, Dominique
Author_Institution :
Presto Eng., Caen, France
Abstract :
This paper presents an original concept of a P+ guard ring realized in a 300μm depth High Resistivity Silicon Substrate (HRS) in order to reduce the substrate noise coupling in a 3D-PICS Integrated Passive Device technology. Guard rings have been designed to be a reliable and efficient protection against noise signals propagation. Case study presented in this work illustrates its significant role. In this paper, a 3D-PICS IPD test chip was studied as a first passive part prototype of a System-In-Package chip in combination with RF transceiver operating in the ISM band (863-870 MHz). Various configurations of the passive chip layout (including implementation of guard rings) have been characterized by Direct Power Injection. 3D-PICS electrical performances deduced from two-ports S-parameters are reported, as well as the guard rings efficiency measurements extracted from these S-parameters. Coupling isolation performances of the new integrated PICS components are found satisfactory.
Keywords :
S-parameters; UHF integrated circuits; coupled circuits; elemental semiconductors; integrated circuit layout; integrated circuit measurement; integrated circuit noise; integrated circuit reliability; integrated circuit testing; passive networks; radio transceivers; silicon; system-in-package; three-dimensional integrated circuits; two-port networks; 3D-PICS IPD test chip; 3D-PICS electrical performance; 3D-PICS integrated passive device technology; HRS; ISM band; P+ guard ring localization; RF transceiver; Si; coupling isolation performance; direct power injection; frequency 863 MHz to 870 MHz; high resistivity silicon substrate; integrated circuit reliability; noise signal propagation; passive chip layout; size 300 mum; substrate noise coupling reduction; system-in-package chip; two-port S-parameter; Attenuation; Capacitors; Couplings; Noise; Phase locked loops; Silicon; Substrates; PICS; coupling; guard ring; integrated passive device; isolation; on-chip crosstalk; substrate noise;
Conference_Titel :
Wireless Sensors and Sensor Networks (WiSNet), 2013 IEEE Topical Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4673-3104-3
Electronic_ISBN :
978-1-4673-2931-6
DOI :
10.1109/WiSNet.2013.6488647
