A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers

We present a carry-select-adder partitioning algorithm for high-performance Booth-encoded Wallace-tree multipliers. By taking into account various data arrival times, we propose a branch-and-bound algorithm and a heuristic to partition an n-bit carry-select adder into a number of adder blocks such that the overall delay of the design is minimized. The experimental results show that our proposed algorithm can achieve on average 9.12% delay reduction with less than 1% of area overhead on 15 multipliers ranges from 16×6-bit to 64×64-bit.