Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications

Author

Jourdain, Anne ; Buisson, Thibault ; Phommahaxay, Alain ; Redolfi, Augusto ; Thangaraju, Sarasvathi ; Travaly, Youssef ; Beyne, Eric ; Swinnen, Bart

Author_Institution

Imec vzw, Leuven, Belgium

fYear

2011

Firstpage

1122

Lastpage

1125

Abstract

Among the many 3D technology options that are being explored today, the 3D-stacked IC approach has become a mature and economically viable technology and provides the highest density for 3D interconnects to date. One approach for IC stacking pursued by imec is the integration of Through Silicon Vias with extreme wafer thinning and backside processing on full CMOS wafers. This has been successfully demonstrated for the first time in a 300 mm production line, and the compatibility of thin wafer handling with backside processing has been evaluated.

Keywords

CMOS integrated circuits; integrated circuit interconnections; passivation; three-dimensional integrated circuits; wafer-scale integration; 3D interconnects; 3D-stacked IC technology; CMOS wafer; TSV integration; backside passivation; production line; size 300 mm; thin wafer handling compatibility; through silicon vias; wafer thinning; Copper; Nails; Passivation; Silicon; Three dimensional displays; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st

Conference_Location

Lake Buena Vista, FL

ISSN

0569-5503

Print_ISBN

978-1-61284-497-8

Electronic_ISBN

0569-5503

Type

conf

DOI

10.1109/ECTC.2011.5898650

Filename

5898650