DocumentCode
1730215
Title
Novel 4F2 DRAM cell with Vertical Pillar Transistor(VPT)
Author
Chung, Hyunwoo ; Kim, Huijung ; Kim, Hyungi ; Kim, Kanguk ; Kim, Sua ; Song, Ki-Whan ; Kim, Jiyoung ; Oh, Yong Chul ; Hwang, Yoosang ; Hong, Hyeongsun ; Jin, Gyo-Young ; Chung, Chilhee
Author_Institution
Semicond. R&D Center, Samsung Electron. Co., Hwasung, South Korea
fYear
2011
Firstpage
211
Lastpage
214
Abstract
New 4F2 cell structure of VPT for the future DRAM devices has been successfully developed by using 30nm process technology. The VPT shows superior current driving capability of 33μA and steep subthreshold slope of 77mV/dec. The VPT device demonstrates excellent retention characteristics in static mode. The floating body effects can be reduced by adopting the gradual junction profile even in a pillar-type channel. Also, the VPT produces about 60% and 30% more gross dies per wafer than conventional 8F2 and 6F2 cells.
Keywords
DRAM chips; nanoelectronics; transistors; 4F<;sup>;2<;/sup>; DRAM cell; DRAM devices; VPT 4F2 cell structure; VPT device; current 33 muA; current driving capability; floating body effects; gradual junction profile; pillar-type channel; size 30 nm; vertical pillar transistor; Computer architecture; Junctions; Logic gates; Microprocessors; Random access memory; Silicon; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European
Conference_Location
Helsinki
ISSN
1930-8876
Print_ISBN
978-1-4577-0707-0
Electronic_ISBN
1930-8876
Type
conf
DOI
10.1109/ESSDERC.2011.6044197
Filename
6044197
Link To Document