A study on poly-Si thin-film transistor (TFT) SONOS memory cells with source/drain engineering

Poly-Si thin-film transistor SONOS memory cells with various source/drain junctions are studied comprehensively. For pure Schottky-barrier junction, the overlap between source/drain and gate is critical. A 2-nm underlap results in high tunneling resistance and thus poor programming efficiency. Suitable designed modified-Schottky-barrier junction can improve programming speed by Fowler-Nordheim tunneling while keeping erase and retention performance unaltered. The main degradation mechanism during endurance test is attributed to interface state generation and tunneling layer degradation. After improving the quality of the tunneling layer, the modified Schottky barrier junction would be a promising choice for 3-dimentional poly-Si memory.