Electrical characterization and impact on signal integrity of new basic interconnection elements inside 3D integrated circuits

Developments in 3D integration technology reveal several basic interconnect elements, as Through Silicon Via, Redistribution Layers, Cu-Pillar and bumps to transmit signals inside 3D circuits. Impact of the interconnect elements on high speed signal integrity all along the global 3D interconnection chain requires investigation. First each element was successively characterized and an equivalent electrical model was extracted in the frequency domain from measurements or simulations. Next these models were realistically chained to simulate the signal integrity performance, declined as delay, of the global 3D-IC interconnection chain in order to determine the best strategies among the multitude of options involved in 3D integration. Three studies were investigated in detail regarding routing strategy, the choice of chip stack orientations (Face-to-Face or Face-to-Back), and the comparison of various 3D technologies available, resulting in global recommendations for future 3D products.