Title :
Study on planarizing process for high aspect ratio via-holes using for electroplating and apply to process for Cu/polyimide multilayer substrates
Author :
Tenmei, H. ; Yamazaki, Tetsuya ; Narizuka, Yasunori
Author_Institution :
Production Eng. Res. Lab., Hitachi Ltd., Yokohama, Japan
Abstract :
A low-cost and high-density circuit board process is developed using Cu electroplating, which flattens uneven surfaces. A circuit board is made using the following process: (1) via-holes are made on a polyimide surface acting as an insulation layer; (2) the metal (Cr/Cu) used to supply the electroplating current is deposited by sputtering; (3) reversed line patterns are made by photolithography; (4) reversed line patterns and via-holes are plugged by simultaneous Cu electroplating; and (5) resist and metal are stripped. This new approach can reduce the number of processes compared with previous methods. However, one problem is that voids occur in the via-holes that have been plugged by the Cu electroplating process. We controlled the electroplating current density and electroplating bath conditions to plug the via-holes without voids. In addition, we fabricated a circuit board with two layers of lines. As a result, this new process has been shown to be capable of manufacturing a high-density circuit board
Keywords :
circuit reliability; copper; current density; electroplating; etching; metallisation; photolithography; photoresists; polymer films; printed circuit manufacture; surface topography; voids (solid); Cr-Cu; Cr/Cu electroplating current supply metallisation; Cu; Cu electroplating; Cu/polyimide multilayer substrates; circuit board; electroplating; electroplating bath conditions; electroplating current density; excess metal stripping; high aspect ratio via-holes; high-density circuit board process; multilayer circuit board; photolithography; planarizing process; polyimide surface insulation layer; resist stripping; reversed line pattern plugging; reversed line patterns; simultaneous Cu electroplating; sputter deposition; uneven surface flattening; via-hole plugging; via-holes; voids; Chromium; Current density; Current supplies; Insulation; Lithography; Polyimides; Printed circuits; Process control; Resists; Sputtering;
Conference_Titel :
IEMT/IMC Symposium, 2nd 1998
Conference_Location :
Tokyo
Print_ISBN :
0-7803-5090-1
DOI :
10.1109/IEMTIM.1998.704626