Application of piezoresistive stress sensor in wafer bumping and drop impact test of embedded ultra thin device

Though an understanding on the development of residual stresses in silicon device after chip level packaging processes has been investigated in previous studies, little is known about the development of stresses after wafer bumping process. In this paper, piezoresistive stress sensors were used to evaluate the stresses in device wafer after wafer bumping process, such as under bump metallization (UBM) fabrication, dry-film process, and solder bumping. For the stress evaluation, n-type piezoresistive stress sensors were fabricated on p-type (100) silicon wafer and then sensors were calibrated to determine piezoresistive coefficients. The calibrated sensor wafers were finally used to measure residual in-plane stresses at the surface of device wafer. Due to the growing demand of portable and handheld devices, the reliability of electronic packages with Pb-free solder under drop impact condition has become an issue of concern. This paper aims to measure the real-time stress in an ultra thin die during a drop test to ascertain whether die cracking is a possible problem when dealing with 50 μm thick dies. The advantages of these stress data are: (1) serve as a basis for process selection to meet the trends and needs of a reliable package, and for the development and improvement of existing processes; and (2) are important to enhance survivability during wafer bumping, handling and packaging.