A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter

Author

Akutagawa, Kazuki ; Machida, Kazuya ; Waho, Takao

Author_Institution

Fac. of Sci. & Technol., Sophia Univ., Tokyo

fYear

2008

Firstpage

174

Lastpage

179

Abstract

A 3/7-level mixed-mode algorithmic analog-to- digital converter (ADC) is proposed. The operation comprises six phases to obtain the 8-bit resolution. The 3-level mode is used in the first three phases for an accurate conversion, while the 7-level mode is used for the last three phases to improve the sampling speed. Transistor-level simulations assuming 0.18-mum CMOS technology with a supply voltage of 1.8 V are carried out to estimate the circuit performance. A signal-to-noise ratio of 48.1dB (ap7.7 bit) is obtained at a sampling frequency of 12.8 MHz, which is superior to the results obtained from conventional 3-level and 7-level algorithmic ADCs.

Keywords

analogue-digital conversion; mixed analogue-digital integrated circuits; 3/7-level mixed-mode algorithmic ADC; CMOS; analog-to-digital converter; frequency 12.8 MHz; size 0.18 mum; transistor-level simulation; voltage 1.8 V; Analog-digital conversion; Approximation algorithms; CMOS technology; Circuit optimization; Circuit simulation; Multivalued logic; Redundancy; Sampling methods; Signal to noise ratio; Voltage; algorithmic; analog-to-digital converter; multiple-valued; redundancy;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple Valued Logic, 2008. ISMVL 2008. 38th International Symposium on

Conference_Location

Dallas, TX

ISSN

0195-623X

Print_ISBN

978-0-7695-3155-7

Type

conf

DOI

10.1109/ISMVL.2008.25

Filename

4539422