A novel process-induced strained silicon (PSS) CMOS technology for high-performance applications

Author

Ko, C.H. ; Ge, C.H. ; Huang, C.C. ; Fu, C.Y. ; Hsu, C.P. ; Chen, C.H. ; Chang, C.H. ; Lu, J.C. ; Yeo, Y.C. ; Lee, W.C. ; Chi, M.H.

Author_Institution

Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan

fYear

2005

Firstpage

25

Lastpage

26

Abstract

We report an optimized process-induced strained silicon (PSS) technology for 90nm CMOS generation and beyond. Through the superposition of various PSS techniques, up to 20% performance enhancement is achieved for both N- and PMOS at channel length down to 45nm. The PSS technology exhibits excellent gate oxide breakdown characteristics, isolation characteristics and reliability. A novel spacer-PSS technology is also proposed for the first time and ∼7% enhancement in ring oscillator speed is observed.

Keywords

MOSFET; elemental semiconductors; nanotechnology; semiconductor device breakdown; silicon; 45 nm; 90 nm; NMOS; PMOS; process-induced strained silicon CMOS technology; spacer-PSS technology; CMOS process; CMOS technology; Capacitive sensors; Compressive stress; Isolation technology; MOS devices; Ring oscillators; Silicon; Space technology; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on

ISSN

1930-8868

Print_ISBN

0-7803-9058-X

Type

conf

DOI

10.1109/VTSA.2005.1497067

Filename

1497067