Title :
A 0.168μm2/0.11μm2 highly scalable high performance embedded DRAM cell for 90/65-nm logic applications
Author :
Wang, G. ; Parries, P. ; Khan, B. ; Liu, J. ; Otani, Y. ; Norum, J. ; Robson, Norman ; Kirihata, T. ; Iyer, Srikanth S.
Author_Institution :
IBM Semicond. R&D Center, Hopewell Junction, NY, USA
Abstract :
A high performance embedded DRAM cell has been developed in 90nm technology using a pass transistor with standard 2.2nm gate oxide and trench capacitor. This device offers 25% on-current improvement with 1.5V wordline boosted voltage, and reduces the cell size by 10%. Measured data retention of >200μs is ideal for 200+MHz random access cycle embedded DRAM macro with a concurrent refresh mode. The scalability of the cell to 0.11 μm2 in 65-nm node is also demonstrated.
Keywords :
DRAM chips; integrated circuit design; logic circuits; nanoelectronics; 1.5 V; 2.2 nm; 200 MHz; 65 nm; 90 nm; DRAM scalability; concurrent refresh mode; embedded DRAM cell; logic applications; Degradation; Design optimization; Doping; Logic devices; Random access memory; Scalability; Subthreshold current; Threshold voltage; Transistors; Tunneling;
Conference_Titel :
VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on
Print_ISBN :
0-7803-9058-X
DOI :
10.1109/VTSA.2005.1497070
