A 90nm generation NOR flash multilevel cell (MLC) with 0.44/spl mu/m/sup 2//bit cell size

Author

Sim, Sang-Pil ; Kwon, Wook Hyun ; Chang Hyun Lee ; Han, Jung In ; Lee, Heon Kyu ; Jung, Cheol ; Heon Kyu Lee ; Jang, Young Kwan ; Park, Se Woong ; Park, Jeung Hwan ; Park, Chan-Kwang ; Kim, Kyung Tae ; Kim, Kinam

Author_Institution

Semicond. R&D Center, Samsung Electron. Co., Ltd., Yongin, South Korea

fYear

2005

Firstpage

35

Lastpage

36

Abstract

A 256Mb NOR MLC flash memory with 90nm technology has been successfully developed. Through judicious integration to control the cell dispersion and charge loss/gain with cycling, we confirm a successful MLC operation up to 10K cycling for 0.44 /spl mu/m/sup 2//bit cell size. In this paper, the key features governing multilevel cell (MLC) operation below 90nm technology node is discussed with experimental results.

Keywords

NOR circuits; flash memories; multivalued logic circuits; 10 K; 256 Mbit; 90 nm; NOR MLC flash memory; NOR circuits; NOR flash multilevel cell; multilevel cell operation; Channel hot electron injection; Flash memory; Interference; Nonvolatile memory; Process control; Research and development; Size control; Stability; Temperature sensors; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on

Conference_Location

Hsinchu

ISSN

1930-8868

Print_ISBN

0-7803-9058-X

Type

conf

DOI

10.1109/VTSA.2005.1497072

Filename

1497072