Effect of low-k dielectric material on 63nm MLC (multi-level cell) NAND flash cell arrays

Author

Park, Mincheol ; Choi, Jung-Dal ; Hur, Sung-Hoi ; Park, Jong-Ho ; Lee, Joon-Hee ; Park, Jin-Taek ; Sel, Jong-Sun ; Kim, Jong-Won ; Song, Sang-Bin ; Lee, Jung-Young ; Lee, Li-Hwon ; Son, Suk-loon ; Kim, Yong-Seok ; Chai, Soo-Jin ; Kim, Kyeong-Tae ; Kim, Ki

Author_Institution

Semicond. R&D Center, Samsung Electron. Co., Ltd., Yongin, South Korea

fYear

2005

Firstpage

37

Lastpage

38

Abstract

We investigate the effect of applying oxide spacer into MLC NAND flash memory with 63nm design rule. The oxide spacer is effective on reducing cell to cell coupling with its low-k dielectric constant. The uniform cell V_th distribution of 0.6V fulfilling the MLC operation is obtained while maintaining fast programming speed and sufficient cell current.

Keywords

NAND circuits; dielectric materials; flash memories; logic arrays; multivalued logic circuits; 0.6 V; 63 nm; MLC NAND flash cell arrays; MLC NAND flash memory; low-k dielectric constant; low-k dielectric material; multilevel cell; oxide spacer; Dielectric constant; Dielectric materials; Dielectric measurements; Doping; Flash memory; Interference; Nonvolatile memory; Silicon; Space technology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on

ISSN

1930-8868

Print_ISBN

0-7803-9058-X

Type

conf

DOI

10.1109/VTSA.2005.1497073

Filename

1497073