• DocumentCode
    1731213
  • Title

    Impact of slurry in Cu CMP (chemical mechanical polishing) on Cu topography of Through Silicon Vias (TSVs), re-distribution layers, and Cu exposure

  • Author

    Chen, J.C. ; Tzeng, P.J. ; Chen, S.C. ; Wu, C.Y. ; Chen, C.C. ; Hsin, Y.C. ; Lau, J.H. ; Hsu, Y.F. ; Shen, S.H. ; Liao, S.C. ; Ho, C.H. ; Lin, C.H. ; Ku, T.K. ; Kao, M.J.

  • Author_Institution
    Electron. & Optoelectron. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
  • fYear
    2011
  • Firstpage
    1389
  • Lastpage
    1394
  • Abstract
    In this study, the optimization of Cu CMP performance (dishing) for removing thick Cu plating overburden due to Cu plating for deep TSVs in a 300mm wafer is investigated. Also, backside isolation oxide CMP for TSV Cu exposure is discussed. In order to obtain a minimum Cu dishing on the TSV region, a proper selection of Cu slurries is proposed for the current two-step Cu polishing process. The bulk of Cu is removed with the slurry of high Cu removal rate at the first step and the Cu surface is planarized with the slurry of high Cu passivation capability at the second step. The Cu dishing can be improved up to 97% for the 10μm-diameter TSVs on a 300mm wafer. The dishing/erosion of the metal/oxide can be reduced with respect to a correspondingly-optimized Cu plating overburden for TSVs and RDLs. Cu metal dishing can be drastically reduced once the Cu overburdens are increased to a critical thickness. For backside isolation oxide CMP for TSV Cu exposure, the results show that the Cu studs of TSVs with a bigger via size still keep in a plateau-like shape after CMP.
  • Keywords
    chemical mechanical polishing; copper; electroplating; elemental semiconductors; isolation technology; silicon; slurries; surface topography; three-dimensional integrated circuits; CMP performance; Cu; Cu exposure; Cu plating; Cu removal rate; Cu topography; Si; TSV region; backside isolation oxide; chemical mechanical polishing; high Cu passivation capability; metal dishing; metal oxide errosion; redistribution layer; slurry; through silicon vias; wafer; Copper; Silicon; Slurries; Surface topography; Surface treatment; Through-silicon vias;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st
  • Conference_Location
    Lake Buena Vista, FL
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-61284-497-8
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2011.5898693
  • Filename
    5898693