Cost-effective lithography for TSV-structures

3D and Through-Silicon Vias (TSV) simplify and speed-up the chip-to-chip communication. The usage will enable manufacturers to increase the device performance, while cost effectively reducing overall size. The key issue for this new technology is a cost-effective drilling of holes into the substrate and the possibility to realize high density multilayer redistribution and bump layers (RDL). The most promising approach is to use photolithography with various thin and thick resist applications to etch the vias by deep reactive ion etching (DRIE) and to build up the RDL applicable on substrates with high topography. The structures to produce TSVs do not seem to be a challenge in nowadays production. The diameters are typically 1 to 50 μm resp. 20 to 200 μm for bumps, while the front-end industry manufactures in 32 node today. But to establish 3D IC and TSV, the production preferably should be capable to provide cost-effective lithography on thinned wafers at competitive price levels. This paper will present a method to expand the current production limits of Mask Aligners. Using special features on the mask in combination with a novel illumination optics, it is possible to increase the throughput, the expose gap and/or decrease the minimum structure size. This kind of technologie will enhance the range of *D wafer level packing lithography applications on high topography substrates. The so called “MO Exposure Optics” from SUSS stabilizes the illumination of mask-aligners and allows to freely shape the angular spectrum of the radiation on the mask. So it is possible to transfer well know principles in projection lithography to mask-aligner lithography like Optical Proximity Correction (OPC) or Source Mask Optimization (SMO). It enables also the usage of binary optical elements to enhance the production of high density TSV and RDL/bump structures.