Analytic analysis of 77 K CMOS minimum channel length

The device limits for 77 K CMOS are calculated using a new analytic solution to Poisson´s equation. Symmetric complementary devices with n/sup +/ polysilicon gate n-channels and p/sup +/ polysilicon gate p-channels are modeled. Laplace´s equation in the gate oxide and Poissons´s equation in the silicon are solved with Dirichlet boundary conditions. The surface potential is rigorously derived by requiring continuity of the potential and normal component of the displacement field. The device channel length limit L/sub min/=74 nm at 77 K is calculated. Carrier freezeout is minimized by the resulting surface channel operation.<>