Title :
Power reduction techniques for an OFDM burst synchronization core
Author :
Kabulepa, L.D. ; Ortiz, A. García ; Glesner, M.
Author_Institution :
Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
fDate :
6/24/1905 12:00:00 AM
Abstract :
The design of the synchronization circuitry constitutes a challenging task in the implementation of a OFDM modem for packet-oriented applications. This paper discusses the suitability and efficiency of low power techniques for the design of a burst-mode OFDM synchronization unit. The architecture and system-level simulations refer to the parameters defined for a HiperLAN/2 environment model. The target technology for the VLSI hardware realization is a standard 0.35 μm CMOS process.
Keywords :
CMOS integrated circuits; OFDM modulation; VLSI; mobile radio; modems; packet radio networks; power consumption; synchronisation; wireless LAN; CMOS process; HiperLAN/2; OFDM; VLSI; burst-mode synchronization; low power techniques; modem; orthogonal frequency division multiplexing; packet-oriented applications; synchronization circuitry; system-level simulations; CMOS technology; Circuits; Fading; Frequency estimation; Frequency synchronization; Hardware; Microelectronics; OFDM; Timing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1009828
