Title :
Parasitic-aware synthesis of RF CMOS switching power amplifiers
Author :
Choi, Kiyong ; Allstot, David J. ; Kiaei, Sayfe
Author_Institution :
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
fDate :
6/24/1905 12:00:00 AM
Abstract :
Parasitic-aware synthesis and optimization techniques are presented for a 0.35 μm CMOS three-stage 1 W 900 MHz class-E power amplifier. Employing bond wire and spiral inductors, it achieves 25 dB gain with 49% drain efficiency from a 3.3 V supply. Simulated annealing optimization is used taking advantage of its ability to escape local minima.
Keywords :
CMOS analogue integrated circuits; UHF power amplifiers; circuit optimisation; power inductors; simulated annealing; 0.35 micron; 1 W; 25 dB; 3.3 V; 49 percent; 900 MHz; CMOS power amplifier; bond wire; class-E power amplifier; parasitic-aware synthesis; simulated annealing optimization; spiral inductors; three-stage power amplifier; Bonding; Circuit synthesis; Design automation; Design optimization; Inductors; Power amplifiers; Radio frequency; Radiofrequency amplifiers; Spirals; Wire;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1009829
