• DocumentCode
    1731554
  • Title

    Application of via post interconnection for build up printed circuit board

  • Author

    Kobayashi, Takeshi ; Itaya, Satoshi ; Ikeda, Koichi ; Kawasaki, Jyunichi ; Honma, Hideo

  • Author_Institution
    Kanto Gakuin Univ., Yokohama, Japan
  • fYear
    1998
  • Firstpage
    312
  • Lastpage
    315
  • Abstract
    Recently, printed circuit boards (PCBs) have been downsized and electronic circuits have become more dense, because of the tendency for electronic component miniaturization. With the shrinkage of PCBs, the build up process has become an important production technique in PCB preparation. For the build up technique, each of the electric circuit layers is electrically connected with via holes. The via holes are metallized by means of electroless plating and electroplating of copper. In the electroless plating process with miniaturization of via hole diameter, if the via hole deposition uniformity is decreased, the electrical reliability between the layers significantly deteriorates. Accordingly, the authors investigated build up printed circuit boards using via posts, which are metallized using the Cu electroplating method. The shear strength between electroplated via posts and electrolessly plated underlayers was evaluated. It was found that electroplated via posts with higher shear strength are obtained by optimization of the pretreatment process and electroplating conditions. In particular, it was important that oxide films on the copper underlayer were removed for improved shear strength
  • Keywords
    assembling; circuit reliability; electroless deposition; electroplating; metallisation; optimisation; printed circuit manufacture; printed circuit testing; shear strength; surface treatment; Cu; Cu electroless plating; Cu electroplating; CuO-Cu; PCB downsizing; PCB preparation; PCB shrinkage; build up printed circuit boards; build up process; build up technique; copper underlayer; electric circuit layers; electrical reliability; electroless plating process; electrolessly plated underlayers; electronic circuit density; electronic component miniaturization; electroplated via posts; electroplating conditions optimization; oxide film removal; pretreatment process optimization; production technique; shear strength; via hole deposition uniformity; via hole diameter miniaturization; via hole electrical connection; via hole metallization; via post interconnection; via post metallization; via posts; Conductive films; Conductors; Copper; Insulation; Integrated circuit interconnections; Metallization; Printed circuits; Production; Resins; Resists;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    IEMT/IMC Symposium, 2nd 1998
  • Conference_Location
    Tokyo
  • Print_ISBN
    0-7803-5090-1
  • Type

    conf

  • DOI
    10.1109/IEMTIM.1998.704666
  • Filename
    704666