DocumentCode :
1731703
Title :
High density printed circuit board using B2itTM technology
Author :
Goto, Kenji ; Oguma, Toru ; Fukuoka, Yoshitaka
Author_Institution :
Toshiba Corp., Tokyo, Japan
fYear :
1998
Firstpage :
316
Lastpage :
320
Abstract :
The authors have developed the B2it printed circuit board. The technology was reported initially in a paper at the IMC meeting in April 1996. Since that time, this technology has been applied to a variety of boards. Among these boards, we report in this paper the B2it application to semiconductor packaging. The product has φ0.2~0.1 mm bumps (fine bumps). In order to produce a multilayer high density printed circuit board, we need to add up each layer with conductive bumps over the base layer, which we call the en bloc laminate process. By repeating the en bloc laminate process multiple times, multilayers and stacked arrays are possible. Signals can go down to internal layers directly from surface pad via bumps. This is effective for substrates such as BGA type packages. With the use of the B2 itTM method, it is possible to omit the outer layer plating process. This is an advantage for fine line patterning, because etching the copper foil alone enables circuit patterning. In addition, we introduced two types of liquid photoresist process: the ED method, and the spin coater liquid photoresist process
Keywords :
assembling; ball grid arrays; etching; foils; integrated circuit interconnections; integrated circuit packaging; laminates; photoresists; printed circuit manufacture; spin coating; 0.1 to 0.2 mm; B2it printed circuit board; B2it technology; BGA type packages; Cu; ED method; base layer; circuit patterning; conductive bumps; copper foil; en bloc laminate process; etching; fine bumps; fine line patterning; high density printed circuit board; internal layers; liquid photoresist process; multilayer high density printed circuit board; multilayers; outer layer plating process; semiconductor packaging; spin coater liquid photoresist process; stacked arrays; surface pad via bumps; Copper; Dielectrics; Laminates; Manufacturing processes; Packaging; Printed circuits; Printing; Resists; Substrates; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
IEMT/IMC Symposium, 2nd 1998
Conference_Location :
Tokyo
Print_ISBN :
0-7803-5090-1
Type :
conf
DOI :
10.1109/IEMTIM.1998.704667
Filename :
704667
Link To Document :
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