An effective floorplan-based power distribution network design methodology under reliability constraints

As the CMOS technology enters the deep sub-micron design era, electromigration and voltage drop issues become more crucial for reliable and high performance ASIC designs. In this paper we present an effective floorplan-based power distribution design methodology for ASIC chips. If compared with other approaches, the main distinction of our approach is that it presents a systematic method to build an initial feasible power distribution network at the post-floorplan stage. Then, by iteratively improving the power distribution network based on simulated evolution, our optimization goal is to minimize the wiring resources under reliability constraints. Experimental data shows that the proposed approach can build robust power distribution networks with fewer routing areas.