DocumentCode :
1732266
Title :
A new group distributed arithmetic design for the one dimensional discrete Fourier transform
Author :
Chen, Hun-Chen ; Guo, Jiun-In ; Jen, Chien-Wei
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
Volume :
1
fYear :
2002
fDate :
6/24/1905 12:00:00 AM
Abstract :
This paper presents a new group distributed arithmetic (GDA) design for the one-dimensional discrete Fourier transform (1-D DFT). We adopt distributed arithmetic (DA) computation and exploit the good features of the cyclic convolution to facilitate an efficient realization of one-dimensional N-point DFT using ROM module with small size, a barrier shifter, and N accumulators. To increase the ROM utilization, we re-arrange the content of ROM into several groups in which all the elements in a group will be accessed simultaneously in accumulating all the DFT outputs in word-parallel and bit-serial manner. It is called the GDA design approach in this paper. To compare the results with the traditional DA design, the design with the proposed approach can reduce significantly both the hardware cost and the propagation delay.
Keywords :
VLSI; convolution; delays; discrete Fourier transforms; distributed arithmetic; ROM module; accumulators; barrier shifter; bit-serial manner; cyclic convolution; group distributed arithmetic design; hardware cost; one dimensional discrete Fourier transform; propagation delay; word-parallel manner; Arithmetic; Convolution; Costs; Design engineering; Discrete Fourier transforms; Hardware; Read only memory; Signal processing algorithms; Systolic arrays; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
Type :
conf
DOI :
10.1109/ISCAS.2002.1009867
Filename :
1009867
Link To Document :
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