DocumentCode :
1732310
Title :
Research on SoC test Compression
Author :
Shao, Jingbo ; Ding, Jinfeng ; Huang, Yuyan ; Zhang, Wei ; Wang, Jianhua
Author_Institution :
Coll. of Comput. Sci. & Inf. Eng., Harbin Normal Univ., Harbin, China
Volume :
1
fYear :
2011
Firstpage :
549
Lastpage :
552
Abstract :
This paper explores SoC test Compression methods, compares the advantages and disadvantages of each method, generalizes the characteristics of every approach, expounds how each method works. The situation suitable for using a specific compression method is given. And the possible prospective is pointed out.
Keywords :
data compression; logic testing; system-on-chip; SoC test compression method; system-on-chip; SoC; test compression; test response; tests stimuli;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Science and Network Technology (ICCSNT), 2011 International Conference on
Conference_Location :
Harbin
Print_ISBN :
978-1-4577-1586-0
Type :
conf
DOI :
10.1109/ICCSNT.2011.6182017
Filename :
6182017
Link To Document :
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