ASIC implementation architecture for pulse shaping FIR filters in 3G mobile communications

Author

Zhu, W.-P. ; Ahmad, M.O. ; Swamy, M.N.S.

Author_Institution

Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada

Volume

1

fYear

2002

fDate

6/24/1905 12:00:00 AM

Abstract

This paper presents two system-on-chip oriented implementation architectures for pulse shaping FIR filters used in 3G mobile communications. One is the look-up-table based distributed arithmetic architecture and the other one a modified multiply and accumulation (MAC) implementation. Both schemes employ the pre-upsampling procedure to minimize the consumption of hardware resources. The proposed architectures have been prototyped with FPGA implementation and can be integrated directly to ASIC products.

Keywords

FIR filters; application specific integrated circuits; cellular radio; digital filters; distributed arithmetic; field programmable gate arrays; pulse shaping circuits; table lookup; 3G mobile communications; ASIC implementation architecture; FPGA implementation; hardware resources; look-up-table based distributed arithmetic architecture; multiply and accumulation implementation; pre-upsampling procedure; pulse shaping FIR filters; system-on-chip oriented implementation architectures; 3G mobile communication; Application specific integrated circuits; Computer architecture; Field programmable gate arrays; Finite impulse response filter; Hardware; Multiaccess communication; Prototypes; Pulse shaping methods; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1009870

Filename

1009870