Title :
A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme
Author :
Kim, Youngjoon ; Sung, Ki-Hyuk ; Kim, Lee-Sup
Author_Institution :
Dept. of EECS, KAIST, Taejon, South Korea
fDate :
6/24/1905 12:00:00 AM
Abstract :
Using a carry-select adder scheme, an adder with small number of stages can operate as fast as an adder with large number of stages. In this paper, a 4-block 5-stage 32-bit pipelined carry-select adder is designed and implemented. The proposed adder operates as fast as a conventional 16-stage 32-bit pipelined ripple-carry adder while the number of registers required is nearly same as a conventional 4-stage pipelined adder. This adder is operated at 1.67 GHz clock frequency in a standard 0.25 μm CMOS technology with 2.5 V supply voltage.
Keywords :
CMOS logic circuits; adders; carry logic; high-speed integrated circuits; pipeline arithmetic; 0.25 micron; 1.67 GHz; 2.5 V; 32 bit; CMOS technology; complementary scheme; pipeline architecture; pipelined carry-select adder; registers; Adders; CMOS technology; Circuits; Clocks; Delay; Energy consumption; Frequency; Pipeline processing; Registers; Voltage;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1009877
