Utility-based dynamic cache resizing

Continuing increases in transistor density are enabling increases in the number of on-chip cores and the size of caches. However very large caches in future systems might not be fully utilised. Under-utilised active caches result in a waste of static power. Off-line profiling of applications to determine optimal cache size and configuration is not practical. As an alternative we propose a simple scheme with limited hardware overhead, to dynamically evaluate the utility of the last level cache slice on each tile and to tune the cache associativity at tile-level granularity. In simulations our tuning scheme achieved an average of 30% of static power saving with a slight 0.6% degradation of IPC.