DocumentCode :
1732657
Title :
Architectural approaches to reduce leakage energy in caches
Author :
Tadas, Shashikiran H. ; Chakrabarti, Chaitali
Author_Institution :
Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
Volume :
1
fYear :
2002
fDate :
6/24/1905 12:00:00 AM
Abstract :
In this paper, we present two methods to reduce leakage energy by dynamically resizing the cache during program execution. The first method monitors the miss rate of the individual subbanks (in a subbanked cache structure) and selectively shuts them if their miss rate falls below a predetermined threshold. Simulations on SPECJVM98 benchmarks show that for a 64K I-cache, this method results in a leakage reduction of 17-69% for a 4 subbank structure and 20-75% for a 8 subbank structure when the performance penalty is <1%. The second method dynamically resizes the cache based on whether the macro-blocks (a group of adjacent cache blocks) are being heavily accessed or not. This method has higher area overhead but greater leakage energy reduction. Simulations on the same set of benchmarks show that this method results in a leakage reduction of 22-81% for the I-cache when the performance penalty is <0.1%, and 17-85% for the D-cache when the performance penalty is <1%.
Keywords :
VLSI; cache storage; integrated memory circuits; memory architecture; microprocessor chips; 64 K; D-cache; I-cache; SPECJVM98 benchmarks; dynamic resizing; leakage energy reduction; macroblocks; microprocessor memory components; program execution; subbanked cache structure; Circuits; Degradation; Delay; Microprocessors; Monitoring; Random access memory; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
Type :
conf
DOI :
10.1109/ISCAS.2002.1009882
Filename :
1009882
Link To Document :
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