Title :
Optimizing finite state machines for system-on-chip communication
Author :
Lahtinen, Vesa ; Kuusilinna, Kimmo ; Hämäläinen, Timo
Author_Institution :
Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland
fDate :
6/24/1905 12:00:00 AM
Abstract :
In this paper, finite state machine (FSM) optimization for a system-on-chip (SoC) interconnection is presented. In the used interconnection architecture, the same interface block is used repeatedly and, therefore, optimization of the interface for synthesis is a very critical implementation issue. However, low-level hand-optimization is not desirable and, therefore, optimization should be performed in the high-level description or automatically in the synthesis process. The results of this paper suggest that design space exploration leads to substantial improvements when constructing complex SoCs. Ideas on how to support this automatically with FSM optimization are shown.
Keywords :
CMOS digital integrated circuits; VLSI; application specific integrated circuits; circuit CAD; field programmable gate arrays; finite state machines; high level synthesis; integrated circuit design; integrated circuit interconnections; ASIC technology; FSM optimization; HIBI interface; SoC interconnection; VLSI; design space exploration; finite state machine optimization; heterogeneous IP block interconnection; high-level description; interconnection architecture; interface block; lookup table based FPGA technology; system-on-chip interconnection; Application specific integrated circuits; Automata; Clocks; Computer architecture; Counting circuits; Field programmable gate arrays; Integrated circuit interconnections; Intellectual property; Space exploration; System-on-a-chip;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1009883
