Integrated process for silicon wafer thinning

A low cost and reliable wafer thinning process for Through Silicon Via (TSV) based three dimensional system in packaging (3D SiP) technology is presented. Silicon wafers were first thinned by means of coarse mechanical grinding with a mesh size of approximately #325, followed by fine mechanical grinding with a mesh size of approximately #2000. When applying a high feed rate to achieve higher material removal rate during the coarse grinding process, the thinned silicon wafer with edge crack was observed. It revealed that the stress on wafer edge contacting with grinding wheel was much larger than those at other locations. Mechanical grinding generated wafer warpage because of damaged layer created during the grinding process. Several stress release treatments, including chemical mechanical polishing (CMP) and dry etching process (plasma etching), were employed to thin silicon wafer and remove the damaged layer. The CMP and dry etching process can remove most of the damage produced by coarse and fine grinding, recovering both the mechanical strength and wafer warpage to their original status and resulting in a smoother surface.