DocumentCode :
1732974
Title :
Design of intra prediction module in H.264 and AVS dual modes video decoder chip
Author :
Xu, Shouheng ; Xing, Yuelin ; Wei, Xianzheng
Author_Institution :
Sch. of Inf. Sci. & Eng., Shandong Univ., Jinan, China
Volume :
2
fYear :
2011
Firstpage :
635
Lastpage :
638
Abstract :
This paper introduces the structure of intra prediction module, which has been implemented with Verilog hardware language, in H.264 and AVS dual modes video decoder chip. Firstly, the video coding standards and their principle are introduced. Then a highly efficient hardware architecture is given based on the analysis of intra prediction algorithm in H.264 and AVS. This design reuses some modules according to the common of H.264 and AVS in architecture and algorithm, in particular the PE processing unit. The parallel pipeline and memory controller are also adopted to enhance the decoding efficiency. Finally, the design passes the FPGA verification, which its results of simulation and synthesis show that the timing and area requirements of chip design are both satisfied.
Keywords :
data compression; field programmable gate arrays; hardware description languages; video coding; AVS dual mode video decoder chip; FPGA verification; H.264; PE processing unit; Verilog hardware language; hardware architecture; intra prediction module; parallel pipeline; Educational institutions; Field programmable gate arrays; Multimedia communication; Random access memory; Standards; Streaming media; System-on-a-chip; AVS; FPGA; H.264; intra prediction; video decoder chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Science and Network Technology (ICCSNT), 2011 International Conference on
Conference_Location :
Harbin
Print_ISBN :
978-1-4577-1586-0
Type :
conf
DOI :
10.1109/ICCSNT.2011.6182046
Filename :
6182046
Link To Document :
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