System level synthesis of many-core architectures using parallel stream rewriting

When designing the software and hardware architecture of many-core systems with hundreds of processors on a single chip, a central problem is the scheduling and binding of work-items to execution units. We present a novel synthesis flow for applications with highly dynamic and unpredictable behaviour, which is based on the concept of parallel stream rewriting. In our model, tasks are self-timed and do not require explicit book-keeping by a central scheduler, so that also dynamic and recursive tasks can be managed and synchronized by local rewriting operations on the stream. Complex examples, evaluated using an FPGA prototype, show the effectiveness of our approach.