DocumentCode :
1733192
Title :
An efficient modeling of the multi-gigabit SSO interference to the pre-driver in the weak power supply system based on the charge exchange domain partitioning technique with intentionally utilizing high power supply impedance
Author :
Oikawa, Ryuichi
Author_Institution :
Renesas Electron. Corp., Kawasaki, Japan
fYear :
2011
Firstpage :
1864
Lastpage :
1869
Abstract :
A mitigation of the multi-gigabit SSO noise interference from the I/O buffer to the pre-driver in a DDR4 interface is demonstrated by utilizing a parasitic low-pass noise filter inside the low-cost wire-bonding packages. By optimizing the mutual inductance between I/O driver´s and pre-driver´s power supplies, the on-die decoupling capacitance of the 32bit DDR4 interface operating at 2133Mbps has been successfully reduced by 66-75% with keeping signal quality. A scaling issue in the SSO noise interference analysis is also addressed in this study by employing a domain partitioning technique based on whether individual power supply is closed or open system on the electrical charge. The design study has demonstrated the advantage of the low-cost wire-bonding packages when used for multi-gigabit single-ended interface, which also suggests the design direction and possibility of the over-2Gbps DDR interface with the wire-bonding packages.
Keywords :
DRAM chips; buffer circuits; circuit noise; circuit optimisation; driver circuits; electric impedance; inductance; interference suppression; lead bonding; low-pass filters; peripheral interfaces; power supply circuits; signal denoising; DDR4 interface; I/O buffer; bit rate 2133 Mbit/s; charge exchange domain partitioning technique; electrical charge; high power supply impedance; inductance optimization; low-cost wire bonding package; multigigabit SSO noise interference mitigation; multigigabit single-ended interface; on-die decoupling capacitance; parasitic low-pass noise filter; pre-driver circuit; signal quality; simultaneous switching output interference; weak power supply system; word length 32 bit; Capacitance; Driver circuits; Impedance; Integrated circuit modeling; Logic circuits; Noise; Power supplies;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st
Conference_Location :
Lake Buena Vista, FL
ISSN :
0569-5503
Print_ISBN :
978-1-61284-497-8
Electronic_ISBN :
0569-5503
Type :
conf
DOI :
10.1109/ECTC.2011.5898769
Filename :
5898769
Link To Document :
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