A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL

This paper describes a methodology for automated insertion of concurrent error detection (CED) circuitry in synthesizable Verilog RTL that allows easy tradeoff between overhead and coverage. The insertion is done at the front-end of the synthesis process which is highly advantageous. Computer-aided design (CAD) tools that support the proposed methodology have been implemented and are described. The CAD tools allow the designer to select from different CED schemes that provide various cost/coverage tradeoffs. The CED circuitry is then automatically inserted into the Verilog design. Experimental results are shown which demonstrate the broad range of design points that the proposed methodology offers the designer to choose from to satisfy cost/coverage requirements. The methodology can be seamlessly integrated into the typical design flow used in industry.