Title :
A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs
Author :
Ney, A. ; Bosio, A. ; Dilillo, L. ; Girard, P. ; Pravossoudovitch, S. ; Virazel, A. ; Bastian, M.
Author_Institution :
Lab. d´´Inf., Univ. de Montpellier II, Montpellier
Abstract :
The usual techniques for memory diagnosis are mainly based on signature analysis. They consist in creating a fault dictionary that is used to determine the correspondence between the signature and the fault models affecting the memory. The effectiveness of such diagnosis methods is therefore strictly related to the fault dictionary accuracy. To the best of our knowledge, most of existing signature-based diagnosis approaches targets static faults only. In this paper, we present a new diagnosis approach that represents an alternative to signature-based approaches. This new diagnosis technique, named history-based diagnosis, makes use of the effect-cause paradigm already developed for logic design diagnosis. It consists in creating a database containing the history of operations (read and write) performed on a faulty memory core-cell. This information is crucial to track the root cause of the observed faulty behavior and it can be used to generate the set of possible fault primitives representing the set of suspected fault models. This new diagnosis method is able to identify static as well as dynamic faults. Although applied to SRAMs in this paper, it can be effective also for other memory types such as DRAMs. Experimental results are provided to prove the efficiency of the proposed methodology in generating a list of suspected faults as well as the location of the faulty components in the memory.
Keywords :
DRAM chips; SRAM chips; fault diagnosis; logic design; DRAM; SRAM; dynamic faults; effect-cause paradigm; fault dictionary accuracy; history-based diagnosis technique; logic design diagnosis; memory core-cell fault; memory diagnosis; signature analysis; signature-based diagnosis approaches; static fault; Databases; Dictionaries; Fault detection; Fault diagnosis; Fault location; Logic design; Random access memory; Robots; Testing; Uniform resource locators;
Conference_Titel :
Test Conference, 2008. ITC 2008. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4244-2402-3
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2008.4700555