Title :
Designing array-based CMOS logic gates by using a feedback control system
Author_Institution :
Coll. of Inf. Technol., United Arab Emirates Univ., Al-Ain, United Arab Emirates
Abstract :
This paper introduces an expedient method for designing nano-scaled CMOS logic gates based on minimum-sized transistor arrays. NAND and NOR with fanins of 2 and 3 have been used to demonstrate the time-efficacy of the method based on a feedback control technique. The gates designed using the proposed scheme show improvement in terms of performance as well of power/energy consumption.
Keywords :
CMOS logic circuits; feedback; logic design; logic gates; transistors; array-based CMOS logic gates; complimentary metal oxide semiconductor logic gates; expedient method; feedback control system; minimum-sized transistor arrays; nanoscaled CMOS logic gates; power-energy consumption; CMOS integrated circuits; Delays; Logic gates; MOSFET; Noise; Vectors; Nano-scale CMOS logic gates; energy consumption; performance; power dissipation; proportional-integral-derivative (PID) feedback control; static noise margin; transistor arrays;
Conference_Titel :
Systems, Man and Cybernetics (SMC), 2014 IEEE International Conference on
Conference_Location :
San Diego, CA
DOI :
10.1109/SMC.2014.6974032
