Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation

In this paper, we investigate the retention time distribution of IBM´s 65nm node embedded DRAM. We demonstrate that subthreshold current is the dominant leakage mechanism that determines data retention time, and the retention distribution can be attributed to array V_t variation. Based on this study, we present a new technique for characterization of across-chip V_t variation. The V_t median value and standard deviation of transfer devices within an eDRAM array are estimated by analyzing the retention characteristics. The evaluation results are confirmed by the parametric test data. The proposed method is fast and can be used to monitor V_t variation in both technology development and manufacture. The impact of array V_t spread on the retention and performance of eDRAM is discussed.