DocumentCode :
1733616
Title :
Cell and network level design of a mixed-mode CNN
Author :
Laiho, Mika ; Paasio, Ari ; Kananen, Asko ; Halonen, Kari
Author_Institution :
Electron. Circuit Design Lab., Helsinki Univ. of Technol., Finland
Volume :
1
fYear :
2002
fDate :
6/24/1905 12:00:00 AM
Abstract :
In this paper cell and network level design of a mixed-mode cellular neural network is shown. First, second and third order polynomial feedback terms are included in the cell and Heun´s integration method is used. In order to reduce the cell count, the array is designed so that it can process input data that has been divided into blocks. The whole input data is stored in parallel with the cells so that all input/output operations during processing are local. Cell structure is shown along with register connections between edge cells of the network. Analog power consumption and computing speed are estimated by HSPICE simulations using 0.25 μm digital CMOS process parameters. The die area of a network with 2*72 cells with 36 layers in each is determined by drawing the layout.
Keywords :
CMOS integrated circuits; cellular arrays; cellular neural nets; integrated circuit design; integrating circuits; mixed analogue-digital integrated circuits; neural chips; polynomials; 0.25 micron; 326 mW; CMOS process parameters; HSPICE simulations; Heun integration method; analog power consumption estimation; array; cell level design; computing speed estimation; mixed-mode CNN; mixed-mode cellular neural network; network level design; second order polynomial feedback terms; third order polynomial feedback terms; Analog computers; Ash; Brain; Cellular neural networks; Computational modeling; Energy consumption; Epilepsy; Feedback; Polynomials; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
Type :
conf
DOI :
10.1109/ISCAS.2002.1009917
Filename :
1009917
Link To Document :
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